This is Intel’s foray into a disaggregated architectural design, with the four tiles connected via Intel’s Foveros 3D packaging. There are a number of firsts here, including the Intel 4 process node at the foundation of the new Compute tile.
Via Intel:
Compute tile – Contains the latest-generation E-cores and P-cores, both of which introduce new microarchitecture enhancements. This tile is built on Intel’s next generation Intel 4 process node bringing major advancements in power-efficient performance.
SOC tile – Integrates a Neural Processing Unit (NPU), bringing power efficient…
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